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STMicroelectronics Introduces STM3220G-JAVA Starter Kit

Posted by Ken Cheung in EDA Tools on Monday, May 14, 2012

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STMicroelectronics introduced the STM3220G-JAVA Starter Kit. The STM3220G-JAVA kit is a complete platform for evaluating the development of embedded applications in Java for the STM32 F2 series microcontrollers. The new Java tool includes an evaluation version of IS2T’s MicroEJ Software Development Kit (SDK) and the STM32F2 series microcontroller evaluation board providing everything engineers need to start their projects. The STM3220G-JAVA Starter Kit is available now. It is priced at $349.

STMicroelectronics Introduces STM3220G-JAVA Starter Kit »

Sigrity Launches XcitePI IO Interconnect Model Extraction

Posted by Ken Cheung in EDA Tools on Monday, May 14, 2012

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Sigrity launched their XcitePI IO Interconnect Model Extraction and Assessment software. The tool provides accurate system-level analysis of high-speed channels and buses by generating precise chip IO power/ground and signal interconnect models. XcitePI IO Interconnect Model Extraction is available on Windows and Linux platforms. Prices start at $108,000 for a 3-year license. The new tool is part of Sigrity’s XcitePI chip-level analysis family that supports both pre- and post-layout design improvement.

Sigrity Launches XcitePI IO Interconnect Model Extraction »

Kontron Introduces COMe Starterkit Ref. Carrier T10

Posted by Ken Cheung in Boards, Busses on Thursday, May 10, 2012

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Kontron introduced their COM Express Starterkit Ref. Carrier T10. The COMe Starterkit features the Kontron COM Express Reference Carrier-i Type 10, 7″ WVGA touch panel, cables, PSU, and sturdy aluminium case. The Kontron COMe Starterkit Ref. Carrier T10 is configured to make evaluation and development of small form factor and mobile applications easy. The Kontron COM Express Starterkit Type 10 with the COM Express Reference Carrier-i Type 10 is available now.

Kontron Introduces COMe Starterkit Ref. Carrier T10 »

Design Automation Conference Features Keynote Speakers from ARM, IBM, Intel, National Tsing Hua University

Posted by Ken Cheung in Events, Training on Wednesday, May 9, 2012

The 49th Design Automation Conference includes keynote speakers from ARM, IBM, Intel and the National Tsing Hua University. DAC 2012 will feature at least 60 technical sessions on recent developments and trends, management practices and new products, methodologies and technologies. This year’s conference will take place at the Moscone Center in San Francisco, California, from June 3-7, 2012. DAC is sponsored by the Association for Computing Machinery (ACM), the Electronic Design Automation Consortium (EDA Consortium), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM’s Special Interest Group on Design.

Design Automation Conference Features Keynote Speakers from ARM, IBM, Intel, National Tsing Hua University »

Real-Time & Embedded Computing Conference Includes MEDS and MILESTONE Events

Posted by Ken Cheung in Events, Training on Tuesday, May 8, 2012

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The Real-Time & Embedded Computing Conference (RTECC) is headed to Boston at the Sheraton Framingham next Tuesday, May 15, 2012. The RTC Group’s event features two keynotes, Android: A Medical Development Perspective (presented by Alan Cohen of Logic PD) and Where’s My Drone?… and other Technology Security Issues for Tactical Military Electronics (presented by Glenn Thoren of Charles Stark Draper Laboratory). RTECC also includes two new co-located events: the Medical Electronic Device Solutions Conference (MEDS) and the Military Electronics Development Conference known as MILESTONE.

Real-Time & Embedded Computing Conference Includes MEDS and MILESTONE Events »

CDNLive! EMEA 2012 to Take Place in Munich, Germany from 14-16 May

Posted by Ken Cheung in Events, Training on Monday, May 7, 2012

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Cadence Design Systems will hold the CDNLive! EMEA user conference from May 14-16 at the Dolce Hotel in Munich/Unterschleissheim. The annual user conference will share fresh new and best practices that address all aspects of design and IP creation, integration, and verification. Attendees of CDNLive! EMEA will get to explore new techniques for realizing advanced silicon, SoC, and systems.

CDNLive! EMEA 2012 to Take Place in Munich, Germany from 14-16 May »

SynaptiCAD Verilog2VHDL Tool Now Supports Verilog 2005

Posted by Ken Cheung in EDA Tools on Thursday, May 3, 2012

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SynaptiCAD rolled out a new version of their Verilog2VHDL tool. The SynaptiCAD V2V tools translate bidirectionally between Verilog and VHDL source code. The translators are are ideal for converting behavioral and/or RTL-level code to a preferred design language. The V2V translation software is available on Windows and Linux. The SynaptiCAD software can be licensed on either a permanent or leased basis, and both floating and node-locked versions are available.

SynaptiCAD Verilog2VHDL Tool Now Supports Verilog 2005 »

Webinar: Solving Isolation Challenges in Power Conversion Applications

Posted by Ken Cheung in Events, Training on Wednesday, May 2, 2012

Analog Devices and Arrow Electronics are teaming together to host a webcast. The webinar will discuss solutions to isolation challenges in power conversion applications. The online seminar is titled, Solving Isolation Challenges in Power Conversion Applications. The webcast will take place at 12 noon EDT on May 16, 2012.

Webinar: Solving Isolation Challenges in Power Conversion Applications »

ANSYS Introduces RedHawk-3DX 20nm Power Sign-off Solution

Posted by Ken Cheung in EDA Tools on Tuesday, May 1, 2012

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ANSYS launched RedHawk-3DX, which is a fourth-generation power sign-off solution. RedHawk-3DX is designed to meet the power, performance and price demands of low-power mobile, high-performance computing, consumer and automotive electronics. RedHawk-3DX extends previous generations’ capabilities to address sub-20 nanometer (nm) designs with 3+ gigahertz performance and billions of gates. It is also architected to support the simulation of emerging chip and packaging technologies using multi-die three-dimensional ICs (3D-ICs) for smart electronic products.

ANSYS Introduces RedHawk-3DX 20nm Power Sign-off Solution »

Cadence TripleCheck IP Validator Simplifies and Automates IP Compliance Testing

Posted by Ken Cheung in Test Solution on Monday, April 30, 2012

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Cadence Design Systems introduced their TripleCheck IP Validator. The test suite supports all major logic simulators, and it provides a simulator-independent native SystemVerilog and/or e coverage database that supports both leading test bench languages. Cadence TripleCheck IP Validator is available now for PCIe Gen 3. Cadence has support for several additional protocols in development for release later this year.

Cadence TripleCheck IP Validator Simplifies and Automates IP Compliance Testing »

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