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Jeyavijayan (JV) Rajendran (How to pronounce my name?)
Graduate Student
Department of Electrical and Computer Engineering
Polytechnic University
6 Metrotech Center, Brooklyn, NY 11201
Phone: (718) 260-4011
jrajen01 AT students DOT poly DOT edu
                  Bio


RESEARCH INTERESTS
Nanoscale architectures
Trusted hardware design
ADVISORS
Ramesh Karri
Garrett S. Rose
EDUCATION
B.E. in Electronics and Communication Engineering, Anna University, Chennai, India, 2008
M.S. in Computer Engineering, NYU-Poly, New York, USA, 2010
Ph.D. in Electrical Engineering, NYU-Poly, New York, USA, (in progress)
AWARDS AND HONORS
  1. Third place in ACM Student Research Competition at DAC 2012
  2. Service Recongnition Award from Intel, Summer 2012
  3. Summer intern at Security Center of Excellence (SeCoE), Intel, May 2012 - Aug 2012
  4. Third place in IT Security for the next generation in Kaspersky American Cup, Nov 2011
  5. Summer intern at Quantum Research Labs in Hewlett-Packard, June 2011 - Sep 2011
  6. Myron M. Rosenthal Award for Best MS Academic Achievement in ECE Department, NYU-Poly, May 2011
  7. Best Student Paper Award in IEEE International Conference on VLSI Design, Jan 2011
  8. First place in Cyber Security Awareness Week - Embedded Systems Challenge, Nov. 2009
  9. Research Fellowship from Fall 2009 to Spring 2013
  10. Teaching Assisstantship from Fall 2010 to Spring 2013 (Check out our hardware security class )
  11. Best Outgoing Student Award, (Undergraduate) May 2008
PROFESSIONAL SERVICES
  1. Reviewer, IEEE Transactions on Computers
  2. Reviewer, IEEE Transactions on Very Large Scale Integration
  3. Reviewer, IEEE Transactions on Information Forensics and Security
  4. Reviewer, IEEE Transactions on Circuits and Systems - II
  5. Reviewer, IEEE Design and Test Magazine
  6. Reviewer, ACM Journal of Emerging Technologies in Computing
  7. Organizer, Embedded Systems Challenge - Cyber Security Awareness Week, 2012
  8. Organizer, Embedded Systems Challenge - Cyber Security Awareness Week, 2011
  9. Organizer, Embedded Systems Challenge - Cyber Security Awareness Week, 2010
Curriculum Vitae (Last updated on Oct 31, 2012)

PUBLICATIONS

PATENTS
  1. Reconfiguring functional path into Trojan detecting Ring oscillators (US Patent 20120278893).
  2. Systems, processes, and computer-accessible medium for providing Logic Encryption using Fault analysis (US Patent filed).

BOOK CHAPTERS
  1. R. Karri, J. Rajendran, and K. Rosenfeld, Trojan Taxonomy, A Book chapter in Hardware Security and Trust.

JOURNALS
  1. J. Rajendran, A. K. Kanuparthi, M. Zahran, S. Addepalli, G. Ormazabal, and R. Karri, Securing processors against insider attacks: a circuit-microarchitecture co-design approach, accepted in IEEE Design and Test Magazine (Special Issue on Trusted SoC with Untrusted Components).
  2. S. Kannan, J. Rajendran, O. Sinanoglu, and R. Karri, Sneak Path Testing of Crossbar-based Resistive Random Access Memories, accepted in IEEE Transactions on Nanotechnology.
  3. H. Manem, J. Rajendran, and G.S. Rose, Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array, IEEE Transactions on Circuits and Systems-I, 59(5), 2012, pp. 1051-1060 (TCAS-I).
  4. H. Manem, J. Rajendran and G.S. Rose, Design Considerations for Multi-Level CMOS/Nano Memristive Memory, ACM Journal of Emerging Technologies in Computing, 8(1), 2012, pp. 6:1--6:22 (JETC).
  5. G.S. Rose, H. Manem, J. Rajendran, R. Karri and R. Pino, Leveraging Memristive Systems in the Construction of Digital Logic Circuits, Proceedings of the IEEE, 100(6), 2012, pp. 2033-2049 (IEEEProc).
  6. J. Rajendran, H. Manem, R. Karri and G.S. Rose, An Energy-Efficient Memristive Threshold Logic Circuit, IEEE Transactions on Computers, 61(4), 2012, pp. 474-487 (TComp).
  7. M. Tehranipoor, H. Salmani, X. Zhang, X. Wang, R. Karri, J.Rajendran, and K. Rosenfeld, Trustworthy Hardware: Trojan Detection and Design-for-Trust Challenges, Computer Magazine, July 2011, pp. 66-74 (Computer Magazine).
  8. R. Karri, J. Rajendran, K. Rosenfeld, and M. Tehranipoor, Trustworthy Hardware: Identifying and Classifying Hardware Trojans, Computer Magazine, Oct. 2010, pp 39-46 (Computer Magazine).

CONFERENCE PAPERS
  1. X. Zhang, K. Xiao, M. Tehranipoor, J. Rajendran, and R. Karri, A study on the effectiveness of Trojan detection techniques using a red team blue team approach, accepted in IEEE VLSI Test Symposium (VTS'13).
  2. J. Rajendran, O. Sinanoglu, and R. Karri, Is Split Manufacturing secure?, accepted in IEEE/ACM Design Automation and Test Conference (DATE'13).
  3. G. Rose, J. Rajendran, N. McDonald, R. Karri, M. Potkonjak, and B. Wysocki, Hardware Security Strategies Exploiting Nanoelectronic Circuits, accepted in IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC'13).
  4. S. Kannan, J. Rajendran, O. Sinanoglu, and R. Karri, Sneak Path Testing of Memristor-based Memories, accepted in IEEE International Conference on VLSI Design(VLSI Design'13).
  5. S. Kannan, J. Rajendran, O. Sinanoglu, and R. Karri, Engineering Crossbar based Emerging Memory Technologies, in the Proceedings of IEEE International Conference on Computer Design, Oct 2012 (ICCD'12).
  6. J. Rajendran, G. S. Rose, R. Karri, and M. Potkonjak, Nano-PPUF: A Memristor-based security primitive, in the Proceedings of IEEE International Symposium on VLSI, Aug 2012, pp. 84-87 (ISVLSI'12).
  7. J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, Security Analysis of Logic Obfuscation, in the Proceedings of IEEE/ACM Design Automation Conference, May 2012, pp. 83-89 (DAC'12).
  8. J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, Applying IC Testing Concepts to Secure ICs, in the Proceedings of Government Microcircuit Applications and Critical Technology, March 2012 (GOMACTECH'12).
  9. J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, Fault-analysis based Logic Encryption, in the Proceedings of IEEE/ACM Design Automation and Test in Europe, March 2012, pp. 953-958 (DATE'12).
  10. J. Rajendran, V. Jyothi, and R. Karri, Red team blue team approach to hardware trust assessment: The embedded systems challenge experience, in the Proceedings of IEEE International Symposium on Computer Design, Oct 2011, pp. 285-288 (ICCD'11).
  11. J. Rajendran, R. Karri, and G.S. Rose, Parallel Memristors: Improving Variation Tolerance in Memristive Digital Circuits, in the Proceedings of IEEE International Symposium on Circuits and Systems, May 2011, pp. 2241-2244 (ISCAS'11).
  12. J. Rajendran, V. Jyothi, O. Sinanoglu, and R. Karri, Design and Analysis of Ring Oscillator-based Design-for-Trust technique, in the Proceedings of IEEE VLSI Test Symposium, May 2011, pp. 105-110 (VTS'11).
  13. J. Rajendran, H. Manem, R. Karri and G.S. Rose, An Approach to Tolerate Process Related Variations in Memristor-based Applications, in the Proceedings of IEEE Symposium on VLSI Design, Jan. 2011, pp. 20-23 (Best Student Paper Award) (VLSIDesign'11).
  14. J. Rajendran, H. Manem, R. Karri and G.S. Rose, Memristor based Programmable Threshold Logic Array, in the Proceedings of IEEE Symposium on Nanoscale Architectures, June 2010, pp. 5-10 (NanoArch'10).
  15. J. Rajendran, H. Borad, S. Mantravadi and R. Karri, SLICED: A Slide based Concurrent Error Detection Technique for Symmetric Block Ciphers, in the Proceedings of IEEE Symposium on Hardware Oriented Security and Trust, June 2010, pp. 70-75 (HOST'10).
  16. J. Rajendran, J. Jimenez, E. Gavas, V. Padman and R. Karri, A comprehensive taxonomy of hardware Trojans, in the Proceedings of IEEE Symposium on Circuits and Systems, May 2010, pp. 1871-1874 (ISCAS'10).
  17. J. Rajendran, H. Manem and G.S. Rose, NDR based threshold logic fabric with memristive synapses, in the Proceedings of IEEE-NANO, 2009, pp. 725-728 (NANO'09).
  18. S. Chandrasekharan, J. Rajendran and A. Annamalai, Data driven security alarm model for embedded applications, Proceedings of IEEE International Conference on Computing, Communication and Networking, 2008 (ICCCN'08).
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