DVCon Panel: Verification planning
Follow Comments
Follow Author
For many people, verification is an art rather than a science. We don’t know when we are done except by using our experience and some metrics to guide us. We don’t really have the tools available to make it an efficient process as Mentor has demonstrated when comparing their graph-based stimulus generation capabilities against their own constrained-random generation. And at a DVCon panel we found out how far behind verification planning is from everything else. Panel moderator John Brennan, product director for verification at Cadence described this as an art form. So the art part is actually art squared and in my book that it makes it very abstract art as we could expect from Picasso.
Why is verification planning so difficult? I think part of the answer goes back to a Breker Verification panel on Tuesday morning where Mark Glasser from Cypress Semiconductor talked about how difficult it is to create the coverage model. He spoke about the length of time it takes to go from an idea of what they want to cover to how to create the necessary observation points in the design that provide confidence that those are indeed covered. In other words we don’t know how to synthesize from an executable set of requirements into the models that have been defined today and as such the cost to create the ad-hoc document and the manual conversion that companies have to perform today is too expensive. Is the problem with the planning tools, the lack of synthesis tools or the coverage model?
At the same time, we all know and accept that if you fail to plan, you plan to fail and thus we have to make use of what is available. One question that was put to the panelists was “How much time will having a verification plan save?” A rather important question for anyone trying to justify the additional time that it will take. None of the panelists had a direct answer. Jason Sprott - Chief Technology Officer for Verilab also had no direct response but did say that if you never create a plan, you give up the opportunity to collect status information and record how you went about verification. That information can be used to improve your processes the next time around.
Ambar Sarkar - Chief Verification Technologist for Paradigm Works said that a verification plan saves you from wasting time and that the primary reason is to make the process more predictable.
Perhaps the most important data point came from Vigyan Singhal - President and CEO of OSKI Technology who talked about the 72 hour challenge they ran at DAC last year. Out of the 72 hours available to them, they spent 6-8 hours planning. He said that while he had never seen people over-plan, he had seen people over-verify because they hadn’t planned enough.
I think another useful snippet was that the plan gives you the ability to prioritize – another comment that also came out of the Breker panel.
Brian Bailey – keeping you covered
If you liked this feature, and would like to see a weekly or bi-weekly collection of related features delivered directly to your inbox, sign up for the IC Design newsletter.
Follow Comments
Follow Author
Loading comments...
To comment please Log In