Lattice Released iCE40 Los Angeles mobileFPGA in Volume Production
Eight devices in the Lattice Semiconductor iCE40 Los Angeles mobileFPGA family have been fully qualified and released into volume production. The low power LP640, LP1K, LP4K and LP8K devices, and the higher performance HX640, HX1K, HX4K and HX8K devices have been production released with 17 different device/package combinations.
Lattice Released iCE40 Los Angeles mobileFPGA in Volume Production »
HuMANDATA Introduces EDA-301 USB-FPGA Board
HuMANDATA introduced their EDA-301 USB-FPGA board. The EDA-301 features the Altera Cyclone IV E FPGA (EP4CE15F17C8N), 5.0 V external input or USB bus power, and 56 user I/O’s, which are divided into two I/O banks. The configurable PCB includes on-board oscillators, user switches and LEDs. It measures 53 mm x 54 mm, and can be easily swapped for a different FPGA/CPLD board.
HuMANDATA Introduces EDA-301 USB-FPGA Board »
PLDA Unveils QuickTCP 10G TCP/IP Stack IP Core for Altera, Xilinx FPGA
PLDA recently introduced their QuickTCP IP, which is a 10Gb TCP/IP Hardware stack IP core. It features an AMBA AXI4 user interface that enables instant integration into either Altera-based or Xilinx-based FPGA designs. PLDA QuickTCP is a 100% RTL designed IP. It is compliant with the IEEE802.3 specification and supporting the ARP, IPv4, ICMP, and TCP protocols. The PLDA QuickTCP IP solution is available now from PLDA.
PLDA Unveils QuickTCP 10G TCP/IP Stack IP Core for Altera, Xilinx FPGA »
X-fest 2012 Technical Seminars Heading to Dallas, Minneapolis, Toronto, Vancouver
Avnet Electronics Marketing is currently holding their X-fest technical seminar series in North America. X-fest 2012 features twelve technical courses based on Xilinx’s new Artix-7, Kintex-7 and Virtex-7 FPGAs, and Zynq-7000 Extensible Processing Platform (EPP) family. There are four remaining cities on the North American schedule: Dallas, Minneapolis, Toronto, and Vancouver.
X-fest 2012 Technical Seminars Heading to Dallas, Minneapolis, Toronto, Vancouver »
Lattice Introduces New Power Management Architecture, Releases Two App Notes
Lattice Semiconductor introduced a new power management architecture. The new in-system upgradable, star topology power management architecture can be used across a wide range of circuit boards requiring over 12 power supply rails. In addition, Lattice also released two new application notes for their Platform Manager devices that will enable engineers to quickly adopt the new architecture.
Lattice Introduces New Power Management Architecture, Releases Two App Notes »
Lattice Semiconductor Packs MachXO2 PLD into 32 QFN Package
Lattice Semiconductor’s MachXO2 family of programmable logic devices (PLD) is available in a new 32 QFN (Quad Flatpack No-leads) package. Engineering samples of the MachXO2-256 in the 32 QFN package are available now. Production-qualified versions will be available in the third quarter of this year. MachXO2 PLDs with 256 LUTs are priced at $0.55 in volumes of 250K units. The programmable devices are supported in Lattice Diamond design software version 1.4.2.
Lattice Semiconductor Packs MachXO2 PLD into 32 QFN Package »
Maxim 1-Wire Security Reference Design Protects Spartan-6 FPGA-Based Designs
Maxim Integrated Products introduced a reference design that will protect Xilinx Spartan-6 field-programmable gate arrays (FPGAs). The reference design features security software (from Maxim or Xilinx) and the Maxim DS28E01-100 1-Wire secure memory device. Engineers can easily add a level of design security to products with the Maxim DS28E01-100 1-Wire secure memory device. In the future, the reference design will support Artix-7, Kintex-7, Virtex-7 and the Zynq-7000 FPGA devices.
Maxim 1-Wire Security Reference Design Protects Spartan-6 FPGA-Based Designs »
Synopsys Debuts Deep Trace Debug for HAPS FPGA-based Prototyping Systems
Synopsys rolled out a new Deep Trace Debug feature for their HAPS FPGA-based prototyping systems. HAPS Deep Trace Debug increases productivity for debugging complex SoCs by enabling prototypers to capture the long signal trace history needed to identify the root cause of design bugs. HAPS Deep Trace Debug support in Synopsys’ Identify RTL debugger software and HAPS Deep Trace Debug SRAM daughter boards is available now.
Synopsys Debuts Deep Trace Debug for HAPS FPGA-based Prototyping Systems »
Altera, Arrow Electronics, and MathWorks to Host DSP Forum
Altera, Arrow Electronics, and MathWorks are hosting the DSP Forum. The event will discuss application-specific digital signal processing design methodologies targeted for Altera FPGAs. DSP Forum will also explain how the combination of DSP Builder’s model-based design flow and MathWorks tools helps implement high-performance floating-point DSP. The one-day event will take place in multiple cities from May 1st to June 7th.
Altera, Arrow Electronics, and MathWorks to Host DSP Forum »
Achronix Speedster22i FPGAs Feature High Density and High Performance Versions
Achronix Semiconductor revealed details of their Speedster22i HD and HP Field Programmable Gate Arrays. The Speedster22i-HP FPGA family is optimized for ultra high performance. The Speedster22i-HD FPGA is optimized for high density. The Speedster22i FPGA Platform uses Intel’s 22nm process technology. Engineering samples of the HD1000 will start shipping in the third quarter of this year. The HD1000 is the world’s largest FPGA. It features over 1 million effective LUTs and 84 Mb of embedded RAM. The remaining HD and HP FPGA devices will be released in the following 12 months.
Achronix Speedster22i FPGAs Feature High Density and High Performance Versions »
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