Bio
I'm an engineer at Google Inc., where I've worked on a number of different areas, including cluster load balancing, finding related academic articles in Google Scholar, failure analysis, RPC-level networking, server performance optimization, power provisioning, energy efficiency, and the design of Google's computing platform.
Prior to Google I was a member of the Research Staff at Digital Equipment Corporation (later acquired by Compaq), where our group did some of the pioneering work on processor and memory system design for commercial workloads (such as database and Web servers). We also designed Piranha, a scalable shared-memory architecture based on single-chip multiprocessing, which helped inspire some of the multi-core CPUs that are now in the mainstream.
Before joining Digital I was one of the designers of the USC RPM, an FPGA-based multiprocessor emulator for rapid hardware prototyping. I've also worked at IBM Brazil's Rio Scientific Center and lectured at PUC-Rio (Brazil) and Stanford University.
I have a Ph.D. degree in Computer Engineering from the University
of Southern California and B.S. and M.S. degrees in Electrical Engineering
from the Pontifícia Universidade Católica, Rio de Janeiro.
Publications
- The Datacenter as a Computer - an introduction to the design of warehouse-scale machines, Luiz André Barroso and Urs Hölzle. Synthesis Series on Computer Architecture, Morgan & Claypool Publishers, May 2009.
- The Case for Energy-Proportional Computing, Luiz André Barroso and Urs Hölzle. IEEE Computer, Vol. 40, No. 12, December 2007.
- Power Provisioning for a Warehouse-sized Computer, Xiaobo Fan, Wolf-Dietrich Weber and Luiz André Barroso. In Proceedings of the 34th ACM International Symposium on Computer Architecture, San Diego, CA, June 2007.
- Failure Trends in a Large Disk Drive Population, Eduardo Pinheiro, Wolf-Dietrich Weber and Luiz André Barroso. In Proceedings of the 5th USENIX Conference on File and Storage Technologies, San Jose, CA, Feb 2007.
- The Price of Performance: An Economic Case for Chip Multiprocessing, Luiz André Barroso. In ACM Queue, September 2005.
- Web Search for A Planet: The Architecture of the Google Cluster, Urs Hoelzle, Jeffrey Dean, and Luiz André Barroso. In IEEE Micro Magazine, April 2003.
- A Detailed Comparison of Two Transaction Processing Workloads, Robert Stets, Luiz André Barroso, and Kourosh Gharachorloo. In Proceedings of the IEEE 5th Annual Workshop on Workload Characterization, Austin, Texas, November 2002.
- Code Layout Optimizations for Transaction Processing Workloads. Alex Ramirez, Luiz André Barroso, Kourosh Gharachorloo, Robert Cohn, Josep Larriba-Pey, P. Geoffrey Lowney, and Mateo Valero. In Proceedings of the 28th ACM International Symposium on Computer Architecture, Goteborg, Sweden, June 2001.
- Managing Complexity in the Piranha Server-Class Processor Design. Robert Stets, Luiz André Barroso, Kourosh Gharachorloo, and Ravishankar Mosur. Workshop on Complexity Effective Design (held as part of ISCA 2001), invited paper, Goteborg, Sweden, June 2001.
- Piranha: Exploiting Single-Chip Multiprocessing. Luiz André Barroso, Kourosh Gharachorloo, Tom Heynemann, Dan Joyce, David Lowell, Harland Maxwell, Joel McCormack, Ravishankar Mosur, Jeff Sprouse, Robert Stets, and Scott Smith. IEEE Computer Magazine, April 2001.
- Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing. Luiz André Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, and Ben Verghese. In Proceedings of the 27th ACM International Symposium on Computer Architecture. Vancouver, CA, June 2000.
- Efficient ECC-Based Directory Implementations for Scalable Multiprocessors. Kourosh Gharachorloo, Luiz André Barroso, and Andreas Nowatzyk. In Proceedings of the 12th Symposium on Computer Architecture and High-Performance Computing (SBAC-PAD 2000), São Pedro, Brazil, October 2000.
- Impact of Chip-Level Integration on Performance of OLTP Workloads. Luiz André Barroso, Kourosh Gharachorloo, A. Nowatzyk, and B. Verghese. In Proceedings of the 6th IEEE International Symposium on High-Performance Computer Architecture (HPCA-6), Toulouse, France, January 2000.
- Performance of Database Workloads on Shared Memory Systems with Out-of-Order Processors. Parthasarathi Ranganathan, Kourosh Gharachorloo, Sarita Adve, and Luiz André Barroso. In Proceedings of the Eighth International Conference on Architecture Support for Programming Languages and Operating Systems (ASPLOS VIII), San Jose, CA, October 1998.
- Memory System Characterization of Commercial Workloads. Luiz André Barroso, Kourosh Gharachorloo, and Edouard Bugnion. In Proceedings of the 25th ACM International Symposium on Computer Architecture (ISCA), Barcelona, Spain, June 1998.
- An Analysis of Database Workload Performance on Simultaneous Multithreaded Processors. Jack Lo, Luiz André. Barroso, Susan Eggers, Kourosh Gharachorloo, Henry Levy, and Sujay Parekh. In Proceedings of the 25th ACM International Symposium on Computer Architecture (ISCA), Barcelona, Spain, June 1998.
- Memory System Performance of Commercial Applications. Luiz André Barroso and Kourosh Gharachorloo. Forefront Magazine, Digital Equipment Corporation, June 1997.
- Design Options for Small-Scale Shared-Memory Multiprocessors. Luiz André Barroso. Ph.D. Thesis, Department of Electrical Engineering - Systems, University of Southern California, September 1996.
- Performance Evaluation of the Slotted-Ring Multiprocessor. Luiz André Barroso and Michel Dubois. IEEE Transactions on Computers, Vol 44, No. 7, July 1995.
- RPM: A Rapid Prototyping Engine for Multiprocessor Systems. Luiz André Barroso, Sassan Iman, Jaeheon Jeong, Koray Oner, Krishnan Ramamurthy and Michel Dubois. IEEE Computer Magazine, February 1995.
- The Design of RPM: An FPGA-based Multiprocessor Emulator. Koray Oner, Luiz André Barroso, Sassan Iman, Jaeheon Jeong, Krishnan Ramamurthy and Michel Dubois. In Proceedings. of the ACM 3rd International Symposium on Field-Programmable Gate Arrays (FPGA 95), Monterey, CA, February 1995.
- The Performance of Cache-Coherent Ring-based Multiprocessors. Luiz André Barroso and Michel Dubois. In Proceedings. of the 20th International Symposium on Computer Architecture, May 1993.
- A Methodology for Performance Evaluation of Parallel Applications in Multiprocessors. Daniel Menasce, Luiz André Barroso. Journal of Parallel and Distributed Computing, January 1992.
- Scalability Problems in Shared-Memory Multiprocessor Systems. Michel Dubois, Luiz André Barroso, Yang-Sao Chen and Koray Oner. In Proceedings of PARLE 92 (Parallel Architectures and Languages Europe), June 1992.
- Delayed Consistency and its Effects on the Miss Rate of Parallel Programs. Michel Dubois, Jin-Chin Wang, Luiz André Barroso, Yang-Sao Chen and Kangwoo Lee. In Proceedings. of the ACM Conference on Supercomputing, November 1991.
- Cache Coherence on a Slotted Ring. Luiz André Barroso and Michel Dubois. In Proceedings. of the 20th International Conference on Parallel Processing, St. Charles, Illinois, August 1991.
- A Methodology for the Performance Analysis of Parallel Applications in Multiprocessors. Luiz André Barroso. M.S. Thesis, Department of Electrical Engineering, Pontifícia Universidade Católica, Rio de Janeiro, August 1989.
- Performance of Processor-Memory Interconnection Networks under Unbalanced Traffic. Luiz André Barroso and Daniel Menasce. Technical Report 084/89, IBM Rio Scientific Center, September 1989.
Talks
- Saving the Planet with Systems Research, keynote address at ASPLOS XIV, Washingon, D.C., March 2009.
- On Warehouse-scale Computers, Distinguished Lecture in Computer Science and Engineering, University of Michigan, Ann Arbor, March 2009.
- Energy-proportional Computing, invited talk at the GSRC Workshop on the Future of Data Centers, August 2008.
- Energy Efficient Operations: Some Challenges and Opportunities, invited talk at Velocity (Web Performance and Operations Conference), Burlingame, CA, June 2008.
- Towards Energy-proportional Computing, invited talk at the Intel SSG Power Summit, Santa Clara, CA, October 2007
- All Watts Considered, keynote address to the International Symposium on Low Power Electronics and Design (ISLPED), Portland, OR, July 2007.
- Warehouse-scale Computers, invited talk at the USENIX Annual Technical Conference, Santa Clara, CA, June 2007.
- A View from Outside the Chip, keynote address to the Intel Micro-architecture Conference, San Diego, CA, June 2007.
- Watts, Faults and other fascinating dirty words computer architects can no longer afford to ignore, Google New York Speaker Series, New York, NY, April 2007.
- Building and Operating a Warehouse-sized Computer, AMD Distinguished Speaker Series, Sunnyvale, CA, March 2007.
- More than One Hammer: dealing with performance, failures and resource management in a large internet service, keynote address to the GSRC Annual Symposium, San Jose, CA, 2006.
- Warehouse-sized Workloads, keynote address to the 2006 IEEE International Symposium on Workload Characterization, San Jose, CA, October 2006.
- Up and Running (FAST), talk delivered at the Computer Science Colloquium at Harvard University and at the RAD Lab at U.C. Berkeley, Fall 2006.
- A Computing Platform for Accessing the World's Information, Invited talk at IBM T.J. Watson Research Center, April 7 2006.
- MIPS, Watts and Dollars, Keynote presentation at the First Workshop on Temperature-Aware Computer Systems (held in conjunction with ISCA-31), Munich, Germany, June 2004.
- Can You Afford High-Performance?, Invited speaker at the Fourth SIGMETRICS Workshop on Software and Performance, Redwood City, California, January 2004.
- Architectural Requirements of Large-Scale Internet Services, Invited keynote address at the 15th Symposium on Computer Architecture and High-Performance Computing, Sao Paulo, Brazil, November 2003.
- The Google Search Engine Room, Invited speaker at the Intel Leadership Forum, Hillsboro, Oregon, June 23, 2003.
- Google: Finding Needles in Terabyte Haystacks, Invited speaker at the Computer Architecture Department, Universidad Politecnica de Catalunya, Barcelona, Spain, July 2002.
- The Google Search Engine Room, Invited speaker at the Intel Leadership Forum, Hillsboro, Oregon, June 23, 2003.
- Google: Finding Needles in Terabyte Haystacks, Invited speaker at the Computer Architecture Department, Universidad Politecnica de Catalunya, Barcelona, Spain, July 2002.
- Designing a Scalable CMP-based System for Commercial Workloads, presented at the 27th Asilomar Microcomputer Workshop, April 2001, Asilomar, CA.
- Piranha: A Complexity-Effective Processor Design for Commercial Workloads, presented at the U.T. Austin Computer Science Department Computer Architecture Seminar series, April 2001.
- The Piranha Project: Designing a Scalable CMP-based System for Commercial Workloads, presented at the Stanford Computer Science Department EE380 Seminar series, February 2001.
- Effectiveness of Off-chip Caches for Commercial Applications, presented at the ISCA Workshop on Scalable Shared-Memory Multiprocessors, Atlanta, GA, April 1999. Co-authored with Ben Verghese (speaker) and Kourosh Gharachorloo.
- Design and Evaluation of Architectures for Commercial Workloads, invited seminar presented at the Department D Arquitectura de Computadors, Universitat Politecnica de Catalunya (UPC), Barcelona, Spain, February 1999.
- Experience with Database Workloads, part of the ASPLOS VIII Tutorial on The Impact of Database System Configuration on Computer Architecture Performance Evaluation, San Jose, CA, October 1998. Co-authored with Kourosh Gharachorloo
- System Design Considerations for a Commercial Application Environment, invited talk presented at the First Workshop on Computer Architecture Evaluation Using Commercial Workloads (held as part of HPCA-4), Las Vegas, NV, February 1998. Co-authored with Kourosh Gharachorloo.
- Hardware Emulation: A New Approach for the Rapid Prototyping of Multiprocessors, invited talk presented at IBM T.J. Watson Research Center and University of Illinois at Urbana-Champaign, March 1995. Co-authored with Michel Dubois, Koray Oner, and Jaeheon Jeong.
- Design and Performance of Shared-Memory Multiprocessors: The Hardware Emulation Approach, presented at the Forth Workshop on Scalable Shared-Memory Multiprocessors (held as part of ISCA 94), Chicago, April 1994. Co-authored with Michel Dubois, Koray Oner and Krishan Ramamurthy.
Patents
- 13 patents on memory system design, single-chip
multiprocesing, coherence protocols, and cache organization (US patent
numbers: 6,751,720; 6,751,710; 6,748,498; 6,738,868; 6,725,343;
6,725,334; 6,697,919; 6,675,265; 6,668,308; 6,640,287; 6,636,949;
6,622,218; 6,622,217)
- Other Google patents filed.