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by Steve Guinta

CAPACITANCE AND CAPACITORS
I. Understanding the Parasitic Effects In Capacitors:

Q. I need to understand how to select the right capacitor for my application, but I’ m not clear on the advantages and disadvantages of the many different types.

A. Selecting the right capacitor type for a particular application really isn’ t that difficult. Generally, you’ ll find that most capacitors fall into one of four application categories:

• AC coupling, including bypassing (passing ac signals while blocking dc)
• decoupling (filtering ac or high frequencies superimposed on dc or low frequencies in power, reference, and signal circuitry)
• active/passive RC filters or frequency-selective networks
• analog integrators and sample-and-hold circuits (acquiring and storing charge)

Even though there are more than a dozen or so popular capacitor types- including poly, film, ceramic, electrolytic, etc.- you’ ll find that, in general, only one or two types will be best suited for a particular application, because the salient imperfections, or “ parasitic effects” on system performance associated with other types of capacitors will cause them to be eliminated.

Q. What are these “ parasitic effects” you’ re talking about?

A. Unlike an “ ideal” capacitor, a “ real” capacitor is typified by additional “ parasitic” or “ non-ideal” components or behavior, in the form of resistive and inductive elements, nonlinearity, and dielectric memory. The resulting characteristics due to these components are generally specified on the capacitor manufacturer’ s data sheet . Understanding the effects of these parasitics in each application will help you select the right capacitor type.

Model of a “ Real” Capacitor

Q. OK, so what are the most important parameters describing non-ideal capacitor behavior?

A. The four most common effects are leakage (parallel resistance), equivalent series resistance (ESR), equivalent series inductance (ESL), and dielectric absorption (memory).

Capacitor Leakage, R_P: Leakage is an important parameter in ac coupling applications, in storage applications, such as analog integrators and sample-holds, and when capacitors are used in high-impedance circuits.

In an ideal capacitor, the charge, Q, varies only in response to current flowing externally. In a real capacitor, however, the leakage resistance allows the charge to trickle off at a rate determined by the R-C time constant.

Electrolytic-type capacitors (tantalum and aluminum), distinguished for their high capacitance, have very high leakage current (typically of the order of about 5-20 nA per µ F) due to poor isolation resistance, and are not suited for storage or coupling applications.

The best choices for coupling and/or storage applications are Teflon (polytetrafluorethylene) and the other “ poly” types (polyproplene, polystyrene, etc).

Equivalent Series Resistance (ESR), R_S: The equivalent series resistance (ESR) of a capacitor is the resistance of the capacitor leads in series with the equivalent resistance of the capacitor plates. ESR causes the capacitor to dissipate power (and hence produce loss) when high ac currents are flowing. This can have serious consequences at RF and in supply decoupling capacitors carrying high ripple currents, but is unlikely to have much effect in precision high-impedance, low-level analog circuitry.

Capacitors with the lowest ESR include both the mica and film types.

Equivalent Series Inductance (ESL), L_S: The equivalent series inductance (ESL) of a capacitor models the inductance of the capacitor leads in series with the equivalent inductance of the capacitor plates. Like ESR, ESL can also be a serious problem at high (RF) frequencies, even though the precision circuitry itself may be operating at DC or low frequencies. The reason is that the transistors used in precision analog circuits may have gain extending up to transition frequencies (Ft) of hundreds of MHz, or even several GHz, and can amplify resonances involving low values of inductance. This makes it essential that the power supply terminals of such circuits be decoupled properly at high frequency.

Electrolytic, paper, or plastic film capacitors are a poor choice for decoupling at high frequencies; they basically consist of two sheets of metal foil separated by sheets of plastic or paper dielectric and formed into a roll. This kind of structure has considerable self inductance and acts more like an inductor than a capacitor at frequencies exceeding just a few MHz.

A more appropriate choice for HF decoupling is a monolithic, ceramic-type capacitor, which has very low series inductance. It consists of a multilayer sandwich of metal films and ceramic dielectric, and the films are joined in parallel to bus-bars, rather than rolled in series.

A minor tradeoff is that monolithic ceramic capacitors can be microphonic (i.e., sensitive to vibration), and some types may even be self-resonant, with comparatively high Q, because of the low series resistance accompanying their low inductance. Disc ceramic capacitors, on the other hand, are sometime quite inductive, although less expensive.

Q. I’ ve seen the term “ dissipation factor” used in capacitor selection charts. What is it?

A. Good question. Since leakage, ESR, and ESL are almost always difficult to spec separately, many manufacturers will lump leakage, ESR and ESL into a single specification known as dissipation factor, or DF, which basically describes the inefficiency of the capacitor. DF is defined as the ratio of energy dissipated per cycle to energy stored per cycle. In practice, this is equal to the power factor for the dielectric, or the cosine of the phase angle. If the dissipation at high frequencies is principally modeled as series resistance, at a critical frequency of interest, the ratio of equivalent series resistance, ESR, to total capacitive reactance is a good estimate of DF,

Dissipation factor also turns out to be the equivalent to the reciprocal of the capacitor’ s figure of merit, or Q, which is also sometimes included on the manufacturer’ s data sheet.

Dielectric Absorption, RDA, CDA: Monolithic ceramic capacitors are excellent for HF decoupling, but they have considerable dielectric absorption, which makes them unsuitable for use as the hold capacitor of a sample-hold amplifier (SHA). Dielectric absorption is a hysteresis-like internal charge distribution that causes a capacitor which is quickly discharged and then open-circuited to appear to recover some of its charge. Since the amount of charge recovered is a function of its previous charge, this is, in effect, a charge memory and will cause errors in any SHA where such a capacitor is used as the hold capacitor.

Capacitors that are recommended for this type of application include the “ poly” type capacitors we spoke about earlier, i.e., polystyrene, polypropylene, or Teflon. These capacitor types have very low dielectric absorption (typically <0.01%).

*The characteristics of capacitors in general are summarized in the capacitor comparison chart below.

A note about high-frequency decoupling in general: The best way to insure that an analog circuit is adequately decoupled at both high and low frequencies is to use an electrolytic-type capacitor, such as a tantalum bead, in parallel with a monolithic ceramic one. The combination will have high capacitance at low frequency, and will remain capacitive up to quite high frequencies. It’ s generally not necessary to have a tantalum capacitor on each individual IC, except in critical cases; if there is less than 10 cm of reasonably wide PC track between each IC and the tantalum capacitor, it’ s possible to share one tantalum capacitor among several ICs.

Another thing to remember about high frequency decoupling is the actual physical placement of the capacitor. Even short lengths of wire have considerable inductance, so mount the HF decoupling capacitors as close as possible to the IC, and ensure that leads consist of short, wide PC tracks.

Ideally, HF decoupling capacitors should be surface-mount parts to eliminate lead inductance, but wire-ended capacitors are ok, providing the device leads are no longer than 1.5 mm.

II. Stray Capacitance:
A. Now that we’ ve talked about the parasitic effects of capacitors as components, let’ s talk about another form of parasitic known as “ stray” capacitance.

Q. What’ s that?

A. Well, just like a parallel-plate capacitor, stray capacitors are formed whenever two conductors are in close proximity to each other (especially if they’ re running in parallel), and are not shorted together or screened by a conductor serving as a Faraday shield.

Capacitor Model

Stray or “ parasitic” capacitance commonly occurs between parallel traces on a PC board or between traces/planes on opposite sides of a PC board. The occurrence and effects of stray capacitance- especially at very high frequencies- are unfortunately often overlooked during circuit modelling and can lead to serious performance problems when the system circuit board is constructed and assembled; examples include greater noise, reduced frequency response, even instability.

For instance, if the capacitance formula is applied to the case of traces on opposite sides of a board, then for general purpose PCB material (E_R = 4.7, d = 1.5 mm), the capacitance between conductors on opposite sides of the board is just under 3 pF/cm². At a frequency of 250 MHz, 3 pF corresponds to a reactance of 212.2 ohms!

Q. So how can I eliminate stray capacitance?

A. You can never actually “ eliminate” stray capacitance; the best you can do is take steps to minimize its effects in the circuit.

Q. How do I do that?

A. Well, one way to minimize the effects of stray coupling is to use a Faraday shield, which is simply a grounded conductor between the coupling source and the affected circuit.

Q. How does it work?

A. Look at the Figure; it is an equivalent circuit showing how a high-frequency noise source, V_N, is coupled into a system impedance, Z, through a stray capacitance, C. If we have little or no control over V_n or the location of Z₁, the next best solution is to interpose a Faraday shield:

As shown, below, the Faraday shield interrupts the coupling electric field. Notice how the shield causes the noise and coupling currents to return to their source without flowing through Z₁.

Another example of capacitive coupling is in side-brazed ceramic IC packages. These DIP packages have a small, square, conducting Kovar lid soldered onto a metallized rim on the ceramic package top. Package manufacturers offer only two options: the metallized rim may be connected to one of the corner pins of the package, or it may be left unconnected. Most logic circuits have a ground pin at one of the package corners, and therefore the lid is grounded. But many analog circuits do not have a ground pin at a package corner, and the lid is left floating. Such circuits turn out to be far more vulnerable to electric field noise than the same chip in a plastic DIP package, where the chip is unshielded.

Whatever the environmental noise level, it is good practice for the user to ground the lid of any side brazed ceramic IC where the lid is not grounded by the manufacturer. This can be done with a wire soldered to the lid (this will not damage the device, as the chip is thermally and electrically isolated from the lid). If soldering to the lid is unacceptable, a grounded phosphor-bronze clip may be used to make the ground connection, or conductive paint can be used to connect the lid to the ground pin. Never attempt to ground such a lid without verifying that it is, in fact, unconnected; there do exist device types with the lid connected to a supply rail rather than to ground!

One case where a Faraday shield is impracticable is between the bond wires of an integrated circuit chip. This has important consequences. The stray capacitance between two chip bond wires and their associated leadframes is of the order of 0.2 pF; observed values generally lie between 0.05 and 0.6 pF.

Consider a high-resolution converter (ADC or DAC), which is connected to a high-speed data bus. Each line of the data bus, (which will be switching at around 2 to 5 V/ns),will be able to influence the converter’ s analog port via this stray capacitance; the consequent coupling of digital edges will degrade the performance of the converter.

This problem may be avoided by isolating the data bus, interposing a latched buffer as an interface. Although this solution involves an additional component that occupies board area, consumes power, and adds cost, it can significantly improve the converter’ s signal-to-noise.

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