EDA Consortium Reports Revenue Increase for Q3 2012
January 7th, 2013
The EDA Consortium (EDAC) Market Statistics Service (MSS) has announced that the Electronic Design Automation (EDA) industry revenue increased 4.9 percent for Q3 2012 to $1619.9 million, compared to $1543.9 million in Q3 2011. Sequential EDA revenue for Q3 2012 increased 1.7 percent compared to Q2 2012, while the four-quarters moving average, which compares the most recent four quarters to the prior four quarters, increased by 8.8 percent.
“The EDA industry recorded its eleventh consecutive year-over-year quarterly growth,” said Walden C. Rhines, board sponsor for the EDAC MSS and chairman and CEO of Mentor Graphics. “Asia/Pacific led the way with double-digit growth, while all other regions except Japan were also positive.”
Companies that were tracked employed 28,877 professionals in Q3 2012, an increase of 6.3 percent compared to the 27,162 people employed in Q3 2011, and up 2.4 percent compared to Q2 2012.
The complete MSS report, containing detailed revenue information broken out by both categories and geographic regions, is available via subscription from the EDA Consortium.
Revenue by Product Category
The largest category, Computer Aided Engineering (CAE), generated revenue of $632.5 million in Q3 2012, which represents an 11.6 percent increase over Q3 2011. The four-quarters moving average for CAE increased 11.0 percent.
IC Physical Design & Verification revenue decreased to $326.7 million in Q3 2012, a 3.4 percent decrease compared to Q3 2011. The four-quarters moving average increased 12.2 percent.
Printed Circuit Board and Multi-Chip Module (PCB & MCM) revenue of $153.0 million represents an increase of 9.0 percent compared to Q3 2011. The four-quarters moving average for PCB & MCM decreased 1.7 percent. Semiconductor Intellectual Property (SIP) revenue totaled $423.0 million in Q3 2012, a 3.2 percent increase compared to Q3 2011. The four-quarters moving average increased 9.0 percent.
Services revenue was $84.7 million in Q3 2012, a decrease of 4.6 percent compared to Q3 2011. The four-quarters moving average decreased 0.8 percent.
Revenue by Region
The Americas remains EDA’s largest region, purchasing $715.7 million of EDA products and services in Q3 2012, an increase of 1.3 percent compared to Q3 2011. The four-quarters moving average for the Americas increased 9.3 percent.
Revenue in Europe, the Middle East, and Africa (EMEA) was up 3.8 percent in Q3 2012 compared to Q3 2011 on revenues of $267.5 million. The EMEA four-quarters moving average increased 7.7 percent.
Third quarter 2012 revenue from Japan decreased 5.1 percent to $243.9 million compared to Q3 2011. The four-quarters moving average for Japan decreased 6.6 percent.
The Asia/Pacific (APAC) region revenue increased to $392.8 million in Q3 2012, an increase of 21.8 percent compared to the third quarter in 2011. The four-quarters moving average increased 21.9 percent.
About the MSS Report
The EDA Consortium Market Statistics Service reports EDA industry revenue data quarterly and is available by annual subscription. Both public and private companies contribute data to the report. Each quarterly report is published approximately three months after quarter close. MSS report data is segmented as follows: revenue type (product licenses and maintenance, services, and SIP), application (CAE, PCB/MCM Layout, and IC Physical Design & Verification), and region (the Americas, Europe Middle East and Africa, Japan, and Asia Pacific), with many subcategories of detail provided. The report also tracks total employment of the reporting companies.
About the EDA Consortium
The EDA Consortium is the international association of companies that provide design tools and services that enable engineers to create the world’s electronic products used for communications, computer, space technology, medical, automotive, industrial equipment, and consumer electronics markets among others. For more information about the EDA Consortium, visit www.edac.org, or to subscribe to the Market Statistics Service, call 408-287-3322 or email mss13@edac.org.
Contact Information
EDA Consortium
www.edac.org
This entry was posted on Monday, January 7th, 2013 at 12:23 pm and is filed under Advertiser, News.
EECatalog Tech Videos
GigOptix-40G DQPSK Demonstration
Cost-Effective Millimeter Signal Analysis Approaches | Agilent Technologies
SDC Management and Verification: What's Missing?
John Blyler Interview on ChipEstimate.TV
Synopsys Discusses its New DDR4 Memory Interface IP
IMS 2012 Keynote on Integrating Design and Test
Paul Estrada discusses the benefits of integrated analog FastSPICE with Tanner EDA tool suite
Semicon West - Jim Feldhan interview
Semicon West - Karen Lightman interview
Semicon West 2012 - Ludo Deferm interview
3D EDA Readiness at Cadence
KLA-Tencor 450mm-Capable Surfscan® SP3 Systems
Chipmakers Adopt Cymer’s SmartPulse™
Chris Mack goes deep (UV)
Power and Reliability Sign-off
"New Verdi³ and the Verdi Interoperability Apps (VIA)", Mark Milligan, VP of Marketing, Springsoft
“What is Driving Lint Usage in Complex SOCs?”, Jim Foley, R&D Manager, Real Intent
"Real Intent Demos, and CDC Issues", Jay Littlefield, Sr. FAE
DAC 2012 Update on AMIQ's DVT IDE - New RTL Design Work Flow Support
Cadence Pattern Matching and DFM signoff success
The Next 25 Years of Innovation - DAC 2012 (Part 3)
Richard Goering Talks With Naresh Sehgal (Intel) and James Colgan (Xuropa) About EDA in the Cloud
The Next 25 Years of Innovation - DAC 2012 (Part 2)
Cadence PCB Signal and Power Integrity 3 Day Event Featuring Robert Hanson
The Next 25 Years of Innovation - DAC 2012 (Part 1)
Why GLOBALFOUNDRIES at 28nm?
Parasoft approaches comprehensive testing for embedded software
Automating embedded software testing with Electric Cloud
DVCon 2012: AMIQ launches "Verissimo" - a verification-centric, UVM-aware SystemVerilog linter
Site Sponsors
Featured White Papers
Calypto Catapult Product Family
Accelerate Time to Rtl, Reduce Verification Effort
The Catapult® high-level synthesis tool empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent, and move up to a more productive abstraction level.Calypto SLEC Product Family
The emergence of consumer electronics is causing a fundamental shift in Register Transfer Level (RTL) design methodologies. The race for time to market has resulted in the adoption and growth of higher level design creation methodologies. In particular, High Level Synthesis (HLS) directly from software models to hardware has become very popular. On the other end of the spectrum, the need to create faster and lower power RTL designs for consumer devices has led to design flows where designers use aggressive techniques for optimizing a given RTL design.
Calypto PowerPro Product Family
With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, both via automated tools as well as manually by the RTL designers.
SmartFusion2 Lowest Power FPGAs
The SmartFusion®2 system-on-chip (SoC) FPGA is differentiated from other FPGAs by its low power capabilities that enable orders of magnitude lower power operation for low duty cycle applications.
Kintex 7 FPGA family: High Performance DDR3 memory throughput achieved by optimization of the memory controller
Taking full advantage of the performances of the 7 Series FPGAs can be done by using the high speed memory controller from Barco Silex, which has been reworked to achieve the highest frequency and efficiency.
Write Assist in Low-Voltage SRAMs
Write assist techniques are now commonly used to lower the minimum operating voltage (Vmin) of an SRAM. One of the key reasons to push the SRAM Vmin lower is to enable efficient Dynamic Voltage and Frequency Scaling (DVFS) to save power. In this paper, we discuss the basics of SRAM faliure mechanisms, fundamentals of write assist techniques, ARM® Artisan® Low Voltage Memory Compilers with the write assist feature and results from GLOBALFOUNDRIES 28nm-SLP memories.
Enea Element®: Simplify Distributed Systems with Frameworks from Enea Element
Distributed systems range from simple multi-threaded applications to multi-slot chassis-based systems to networked clusters of servers. Topologies get more complex when these systems move into cloud-based environments, and more diverse when they involve machine-to-machine (or M2M) solutions. Providers of distributed system software solutions face a number of challenges in building, debugging and maintaining a set of connected applications. Managing these systems requires powerful modeling and a variety of management interfaces to meet a diverse set of needs. The services provided by a distributed system often require a high level of availability. The middleware frameworks that make up Enea Element address many of these challenges.
Upcoming Events
-
Cadence User Conference 2013
Silicon Valley, USA March 12 - 13, 2013
-
RTECC Real-Time and Embedded Computing Conference
Dallas, TX March 19th, 2013
-
DATE 2013
Grenoble, France March 18th - 22nd, 2013
-
Successful Fabless Semiconductor 2013
Novotel Vaugirard, Paris April 10 - 12, 2013
-
Design West
San Jose, CA April 22-25, 2013