MIPS Instruction Reference
This is a
description of the MIPS instruction set, their meanings, syntax, semantics, and
bit encodings. The syntax given for each instruction refers to the assembly language
syntax supported by the MIPS assembler. Hyphens in the encoding indicate
"don't care" bits which are not considered when an instruction is
being decoded.
General
purpose registers (GPRs) are indicated with a dollar
sign ($). The words SWORD and UWORD refer to 32-bit signed and 32-bit unsigned
data types, respectively.
The
manner in which the processor executes an instruction and advances its program
counters is as follows:
- execute the
instruction at PC
- copy nPC
to PC
- add 4 or the branch
offset to nPC
This
behavior is indicated in the instruction specifications below. For brevity, the
function advance_pc (int)
is used in many of the instruction descriptions. This function is defined as
follows:
void advance_pc (SWORD offset)
{ PC = nPC;
nPC += offset;
}
Note: ALL arithmetic immediate values are sign-extended. After that,
they are handled as signed or unsigned 32 bit numbers, depending upon the
instruction. The only difference between signed and unsigned instructions is
that signed instructions can generate an overflow exception and unsigned
instructions can not.
The
instruction descriptions are given below:
ADD – Add (with overflow)
|
Description:
|
Adds two registers and stores the result in a
register
|
|
Operation:
|
$d = $s + $t; advance_pc
(4);
|
|
Syntax:
|
add $d, $s, $t
|
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Encoding:
|
0000 00ss ssst tttt dddd d000 0010 0000
|
ADDI -- Add immediate (with overflow)
|
Description:
|
Adds a register and a sign-extended immediate value and
stores the result in a register
|
|
Operation:
|
$t = $s + imm; advance_pc (4);
|
|
Syntax:
|
addi $t, $s, imm
|
|
Encoding:
|
0010 00ss ssst tttt iiii iiii
iiii iiii
|
ADDIU -- Add immediate unsigned (no overflow)
|
Description:
|
Adds a register and a sign-extended immediate value
and stores the result in a register
|
|
Operation:
|
$t = $s + imm; advance_pc (4);
|
|
Syntax:
|
addiu $t, $s, imm
|
|
Encoding:
|
0010 01ss ssst tttt iiii iiii
iiii iiii
|
ADDU -- Add unsigned (no overflow)
|
Description:
|
Adds two registers and stores the result in a
register
|
|
Operation:
|
$d = $s + $t; advance_pc
(4);
|
|
Syntax:
|
addu $d, $s, $t
|
|
Encoding:
|
0000 00ss ssst tttt dddd d000 0010 0001
|
AND -- Bitwise and
|
Description:
|
Bitwise ands two registers and stores the result in
a register
|
|
Operation:
|
$d = $s & $t; advance_pc
(4);
|
|
Syntax:
|
and $d, $s, $t
|
|
Encoding:
|
0000 00ss ssst tttt dddd d000 0010 0100
|
ANDI -- Bitwise and immediate
|
Description:
|
Bitwise ands a register and an immediate value and
stores the result in a register
|
|
Operation:
|
$t = $s & imm; advance_pc (4);
|
|
Syntax:
|
andi $t, $s, imm
|
|
Encoding:
|
0011 00ss ssst tttt iiii iiii
iiii iiii
|
BEQ -- Branch on equal
|
Description:
|
Branches if the two registers are equal
|
|
Operation:
|
if $s == $t advance_pc
(offset << 2)); else advance_pc (4);
|
|
Syntax:
|
beq $s, $t, offset
|
|
Encoding:
|
0001 00ss ssst tttt iiii iiii
iiii iiii
|
BGEZ -- Branch on greater than or equal to zero
|
Description:
|
Branches if the register is greater than or equal to
zero
|
|
Operation:
|
if $s >= 0 advance_pc
(offset << 2)); else advance_pc (4);
|
|
Syntax:
|
bgez $s, offset
|
|
Encoding:
|
0000 01ss sss0 0001 iiii iiii iiii iiii
|
BGEZAL -- Branch on greater than or equal to zero and link
|
Description:
|
Branches if the register is greater than or equal to
zero and saves the return address in $31
|
|
Operation:
|
if $s >= 0 $31 = PC + 8 (or nPC
+ 4); advance_pc (offset << 2)); else advance_pc (4);
|
|
Syntax:
|
bgezal $s, offset
|
|
Encoding:
|
0000 01ss sss1 0001 iiii iiii iiii iiii
|
BGTZ -- Branch on greater than zero
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Description:
|
Branches if the register is greater than zero
|
|
Operation:
|
if $s > 0 advance_pc
(offset << 2)); else advance_pc (4);
|
|
Syntax:
|
bgtz $s, offset
|
|
Encoding:
|
0001 11ss sss0 0000 iiii iiii iiii iiii
|
BLEZ -- Branch on less than or equal to zero
|
Description:
|
Branches if the register is less than or equal to
zero
|
|
Operation:
|
if $s <= 0 advance_pc
(offset << 2)); else advance_pc (4);
|
|
Syntax:
|
blez $s, offset
|
|
Encoding:
|
0001 10ss sss0 0000 iiii iiii iiii iiii
|
BLTZ -- Branch on less than zero
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Description:
|
Branches if the register is less than zero
|
|
Operation:
|
if $s < 0 advance_pc
(offset << 2)); else advance_pc (4);
|
|
Syntax:
|
bltz $s, offset
|
|
Encoding:
|
0000 01ss sss0 0000 iiii iiii iiii iiii
|
BLTZAL -- Branch on less than zero and link
|
Description:
|
Branches if the register is less than zero and saves
the return address in $31
|
|
Operation:
|
if $s < 0 $31 = PC + 8 (or nPC
+ 4); advance_pc (offset << 2)); else advance_pc (4);
|
|
Syntax:
|
bltzal $s, offset
|
|
Encoding:
|
0000 01ss sss1 0000 iiii iiii iiii iiii
|
BNE -- Branch on not equal
|
Description:
|
Branches if the two registers are not equal
|
|
Operation:
|
if $s != $t advance_pc
(offset << 2)); else advance_pc (4);
|
|
Syntax:
|
bne $s, $t, offset
|
|
Encoding:
|
0001 01ss ssst tttt iiii iiii
iiii iiii
|
DIV -- Divide
|
Description:
|
Divides $s by $t and stores the quotient in $LO and
the remainder in $HI
|
|
Operation:
|
$LO = $s / $t; $HI = $s % $t; advance_pc
(4);
|
|
Syntax:
|
div $s, $t
|
|
Encoding:
|
0000 00ss ssst tttt 0000 0000 0001 1010
|
DIVU -- Divide unsigned
|
Description:
|
Divides $s by $t and stores the quotient in $LO and
the remainder in $HI
|
|
Operation:
|
$LO = $s / $t; $HI = $s % $t; advance_pc
(4);
|
|
Syntax:
|
divu $s, $t
|
|
Encoding:
|
0000 00ss ssst tttt 0000 0000 0001 1011
|
J -- Jump
|
Description:
|
Jumps to the calculated address
|
|
Operation:
|
PC = nPC;
|