News (7/3)

Emulator updates

I've decided to switch licenses for SMS Plus, Genesis Plus and TGEmu to the MAME license, in an effort to curb people from selling them for profit. The newest releases are here:

• Genesis Plus v1.3
• SMS Plus v1.6
• TGEmu v0.2

Old News (6/27)

YMO Live

I had a great opportunity to see Yellow Magic Orchestra perform at the Warfield in SF. Its been thirty years since they last visited the USA, and this was quite a limited tour with only one other stop at the Hollywood Bowl in LA. The crowd had a lot of energy and we made enough noise at the end to get two more songs as an encore.

They played more material from their middle period which happens to be my favorite, such as Seoul Music, Taiso, Gradated Grey, and Ongaku. The new songs were fantastic, and of course they covered all the classics the fans were expecting, including an especially rousing performance of Firecracker. Definitely a once in a lifetime chance and a lot of fun!

News (6/26)

Super Magic Drive Schematics

Here are schematics for the floppy disk drive PSU that comes with the Super Magic Drive. What's interesting is that the parts for the +12V rail are missing but could be added. I guess modern 3.5" drives only need +5V to operate? The disk drive itself is identical to a standard PC floppy drive, mine is a TEAC FD-235HF in particular.

• Magic Drive 3.5" schematics (PNG)
• Magic Drive 3.5" schematics (BSch CE3)

PAL device reader, rev. 4

• PAL device reader project files

Atmel ATDH1150USB JTAG cable

• JTAG-A - Connects to a JTAG header to program ATF1508 CPLDs.
• JTAG-X - Same as "A", but as a fine pitch connector.
• TWI (AT17) - Connects to a TWI header to program the AT17xxx FPGA configuration EEPROMs.

• Unlit - Default state when cable is plugged in to a PC.
• Green - Only after the Atmel ISP software has detected the cable and is idle.
• Orange - When communicating with a device (e.g. during programming, erasing, verify)
• Red - When an error has occurred.

You can access the EEPROM data using FTDI's FT Prog v2.2 utility program. Start it and hit F5 (or select "Scan and Parse") to read the device settings. According to the program, the FT2232 is set up like so:

    Chip type:  FT2232D/C
    Vendor ID:  0x0403
    Product ID: 0x6010
    Product Description: 'ATDH1150USB'
    Serial Number: FTS8GSG1 Auto-Generate

The software used is Atmel ISP v6.7, and it's quite well written. Once you set up a chain file to program the device, you can just click on the "Jedec file" chain item and click "OK" on the Device Property dialog box that comes up to automatically reload a new JED file. This makes development very easy and rapid. So overall it's a good product, but I'm sure cheaper options exist.

CPLD development board

• 6-bit (2:2:2 RGB) video DAC (can directly drive a RGB monitor)
• 7-bit audio DAC (can drive a line-in input of an amplifier)
• JTAG header
• Socket for Flash/NVRAM (512K max)
• SD card interface
• Pushbutton and LED (for user I/O)
• Two 2x32 headers to access CPLD pins
• 5V and 3.3V power supply (with power switch and PTC resettable fuse)
• 28.636 MHz clock

SMS Region Mod + YM2413 sound

• Region mod schematic (PNG)

I also implemented this modification in a 16V8 PAL along with the support functions to add YM2413 sound output:

Here are the relevant files:

• Region mod + FM sound schematic (PNG)
• Region mod + FM sound PLD source
• Region mod + FM sound JEDEC fusemap

News (6/11)

System 16 odds and ends

I've updated the Sega USB Link project files with a USB BIOS for the System 16B 171-5797 ROM board, and a sample program (memory map viewer) that can be used as a basis for developing System 16B software.

• Sega USB Link project files

DRAM interface

• AEX# (CN4 A20) - Lags 68K AS# by 10 ns. Can be used by an external multiplexer to switch from the row address to the column address.
• CAS# (CN4 A21) - Lags 68K AS# by 90 ns. Can be used as the column address strobe by DRAMs mapped to the program ROM space. Note: AS# functions as RAS#.

Video ROM access

There are also two additional signals that decouple sprite and tile ROM address bus from the video chips:

• XGAO# (CN2 A20) - When high, disables output of the '374 at J16 that normally connects VR0-7 to GA3-10. This pin is input by the 315-5192 chip and may direct it to tristate the GA0-2 and GA11-15 outputs as well. GA0-15 can then be freely driven.
• OBAC# (CN2 B20) - When high, disables both '244s at J6,J7 that normally connect RD0-15 to RDB0-15. RDB0-15 can then be freely driven. CGB0-3 would still need to be isolated from the sprite ROM banking circuit on the ROM board.

If the object and tile ROMs were replaced with SRAMs, these functions greatly simplify the hardware needed for the 68000 to share the SRAMs with the video hardware, allowing it to write new graphics data as needed. Hang-On supports SRAM in place of sprite ROM, so it seems likely they wanted to support a similar feature for System 16B.

ADPCM mute control

One bit of the Z80 sound bank latch drives the mode input of the uPD7759. This always seemed unusual as the stand-alone mode can't possibly work; the chip's message select inputs (I0-7) are grounded and the message start strobe (ST#) is permanently inactive. Not to mention the lack of external ROMs and support hardware needed to address sample data.

But the designers did this intentionally. In stand-alone mode the chip drives the Z80 data and write pins which would cause a conflict, so they added buffers to isolate these signals. Now the chip can operate in either mode, but uPD7759 manual says the mode pin should never be changed during speech synthesis or when idle; as these are the only two states it has, this seems to imply it shouldn't be changed at all and should be fixed to a desired level at power-up. So why toggle the operating mode during gameplay?

A quirk of ADPCM encoding is that you cannot immediately transition from one volume level to another, it takes several samples to accomplish that. This is problematic when you want to cancel playback of an existing sample and start up another. It would be too hard to calculate the sample data needed to transition from the current state to a new one (if interrupting a sample) or to zero (if muting an existing sample early) and there might be some unusual sounds during the transition period.

So the result of cycling in and out of stand-alone mode seems to mute the chip instantly and reset the internal ADPCM decoding state such that new sample data can be sent. Games pulse the pin high after sample playback ends, transitioning it into stand-alone mode for a few microseconds. In some cases they leave it high until the next sample is requested. For whatever reason the RESET# pin isn't used for this purpose; perhaps asserting it during playback causes an audible pop or other undesired noise. Or maybe it was too complex to add a circuit to assert the pin for the required time (18.7us), and this solution used less parts at the expense of operating the chip in an undefined way.

News (5/8)

TMS9929A experiments

The TMS9918A VDP has composite video output, and the TMS9928A and TMS9929A have component video output in the form of luma (Y) and color difference (R-Y, B-Y) signals. As the luma output includes sync information, it can be used for composite video too, if you don't mind being limited to a grayscale display. The VDP can generate about eight unique shades.

I tried using the composite video output circuit from the Elf Color Board which was intended for TMS9918A/TMS9118A chips, and it worked perfectly on the TMS9929A. Here's a slightly modified schematic of the circuit, along with a test pattern display for the SC-3000 personal computer which has an integrated VDP register editor.

• Composite video output schematic
• Video test pattern and register editor program (Source included)

I'm currently working on a project to add RGB output to the TMS9929A and adapting it to use standard SRAM instead of several 16Kx1 DRAMs. I'll post more information if the experiments are successful.

Old News (4/10)

DECO cassette drive overview

Data East made an arcade system that loaded game data from a miniature cassette, that was played back from a custom digital tape drive. The drive chipset was develped by Mag-Tek who are still in business and make magnetic strip based products. I was asked to look into how the cassette system works so that games could be dumped and preserved. I'll present an overview of the hardware and an (untested) dumping circuit.

The cassette drive connects to the "BIO-8" circuit board by means of a 2x10 pin connector:

                    +----------+
     TAPE_SENSE     |A1 <   B1 |    (N.C.)
     (N.C.)         |A2     B2 |    (N.C.)
     RCLOCK         |A3     B3 |    RDATA
     GND            |A4     B4 |    (N.C.)
     REV            |A5     B5 |    FWD
     FAST           |A6     B6 |    (N.C.)
     (N.C.)         |A7     B7 |    (N.C.)
     EOT/BOT        |A8     B8 |    (N.C.)
     +12V           |A9     B9 |    +12V
     GND            |A10    B10|    GND
                    +----------+

Cable "E" has a 2x10 header that plugs into this connector, and it has a black plastic arrow molded on it which points to pin A1 as shown above. The other end of the cable is a green edge connector with gold contacts that plugs into the cassette drive PCB.

TAPE_SENSE is a switch output that is 5V when a cassette is inserted and the lid is closed, and 0V when no cassette is inserted or the lid isn't closed. The switch is a spring-loaded metal pin near to the motor.

FWD, REV, and FAST are inputs that control the cassette spindle motor when driven at +5V and are inactive at 0V. FWD and REV cannot be asserted at the same time, and the BIO-8 board has logic to prevent this condition. Normally the cassette speed is appropriate for playback when only FWD or REV are driven, and asserting FAST along with either one of those signals is used for a fast-forward or fast-reverse.

RCLOCK and RDATA are the digital data that is encoded on the tape. The clock signal is used to determine when the data signal can be sampled. These outputs are 5V for a '1' bit and 0.40V for a '0' bit. Because the tape passes by the pickup head faster as one spindle gathers tape, the clock and data rate increase during playback. It seems that the MCU on the BIO-8 board is fast enough to handle the steadily increasing data rate.

DECO cassette drive dumping

I have developed a circuit that is connected to the cassette drive cable "E" by splicing the RCLOCK and RDATA wires so that the signal can be tapped. RCLOCK is a white wire at the ends with a gray sleeve and RDATA is a red wire at the ends with a black sleeve. You can also splice the black wire with the foil "E" label on it (corresponding to position A10 on the above diagram) for ground. The circuit should allow normal operation of the board in addition to providing audio outputs for dumping.

It converts the output levels to 1.25V, low-impedance outputs that should be suitable for driving the line-in input of a PC sound card. To prevent damage, I would recommend connecting the outputs to a cheap amplifier first, which you can use to adjust the volume. For this reason the schematic only shows RCA jacks.

• Schematic image

Note that cable "E" has no +5V line, so you'll need to tap that from the PSU that powers your DECO boardset.

PAL TurboGrafx information

NEC released a PAL variant of the TurboGrafx-16 (model HES-TGX-11), which is fairly amusing as the video chipset only supports NTSC. To accomodate PAL displays, a chip (PCZ80 by NHE) clocks the VCE slowly during several scanlines such that a 264-line NTSC frame fits within a 313-line PAL frame. While it can control the CPU speed, it does not slow it down. This means NTSC software has more time to execute code during the "slow" lines, but in practice this does not seem to cause any problems. During the slow lines, the PCZ80 chip continues to generate regular horizontal sync pulses on its composite sync output, such that all 313 lines are present for a PAL monitor.

The video output is fairly interesting. Analog RGB from the VCE is fed into a CXA1145 encoder that is hardwired to PAL mode. It generates S-Video and composite video, the latter of which goes to a 5-pin DIN jack with an unusual 270-degree pin spacing. The S-Video is not accessible but appears to be fully implemented. The composite video output of the VCE is completely bypassed. To provide PAL compatible display timing, the PCZ80 chip generates a 4.48 MHz color subcarrier for the CXA1145 chip.

This arrangement introduces a few subtle differences. The color subcarrier strip bit in the VCE control register does nothing as now the CXA1145 controls the color burst. The frame size bit (262 or 263 lines) does nothing either as the PCZ80 forces a NTSC frame to always be 264 lines. Games that use the vertical blanking interrupt have slow music, those that use the timer do not. No games were reprogrammed to handle PAL differences, and regular North American TurboChips run on the PAL system, albeit letterboxed and slower.

The A/V connector has the following pinout (with the system's connector facing you, pins are 5 to 1 from the 270 degree position going clockwise to the -90 degree position):

    1. Composite video
    2. Right audio
    3. Ground
    4. +5V DC
    5. Left audio
    

• Solder a wire from the side of R155 facing the backplane connector to DIN pin 1.
• Solder a wire from the side of R150 facing the backplane connector to DIN pin 2.
• Solder a wire from DIN pin 3 to the shield ground tab nearest to it on the board perimeter.
• While it isn't necessary to connect +5V, you can solder a wire from the pin of L109 nearest to the board perimeter to pin 4 for compatibility.
• Solder a wire from the side of R149 facing away from the backplane connector to DIN pin 5.

There isn't much information about the PCZ80, though sources seem to indicate it is a Z80-based microcontroller. However it generates complex high-frequency signals, so either it has a very capable timer peripheral or it isn't a MCU at all, and is some kind of small-scale gate array. Relevant pins are:

Pin 2 - Reset input.
Pin 4 - Unused (active-high horizontal sync output)
Pin 5 - Unused (active-low horizontal sync output)
Pin 6 - 21.32825 MHz clock input (X201 via 74HCU04)
Pin 10 - 17.73448 MHz clock input (X202 via 74HCU04)
Pin 11 - 4.48 MHz clock output to CXA1145 "XO IN" (X202/4)
Pin 15 - 21/17 MHz clock output to HuC6260A
Pin 16 - Composite sync output to CXA1145 "C-SYNC IN"
Pin 17 - Vertical sync input from HuC6270
Pin 22 - 21.32825 MHz clock output to HuC6280A

While not fully implemented, to modify a PAL system to NTSC make the following changes: