Training & Services

This course covers the most important aspects of setting up the Analog Designer tool. It covers setting pointers to models libraries as well as how to develop new libraries and manipulate models. The functionality of the Analog Waveform Displayer (AWD) is described in detail, as well as the Waveform Calculator. All the domain analysis functionality is thoroughly explored, as well as statistical analysis.

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Starting with the 20nm processing node, the use of two masks to print a single layer becomes a requirement because of lithography issues. This course will help you understand the impact of double patterning on your designs and how to use Calibre to find and fix layout problems associated with this approach.

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Calibre® eqDRC represents an important breakthrough in physical verification, making it possible for anyone performing design rule and LVS checks to truly do more with less.

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Layout Versus Schematic (LVS) verification has always played a critical role in the IC design process. Calibre nmLVS continues to be the pre-eminent tool for this task. Recent Calibre enhancements have significantly extended the tool’s capabilities and have helped to streamline the LVS debugging task. This course will introduce you to all of these new features through a series of LVS case studies.

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This course will help you understand the wide breadth of problem areas addressed by Calibre PERC, including ESD, advanced ERC, multiple power domains, point-to-point resistance, and current density.

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This class teaches students how to create custom Calibre DRV scripts and batch files that can be used to analyze and manipulate layout data. This class also teaches students how to extend the Calibre DRV GUI to obtain user input, display results from running DRV scripts, and add menus and menu items to invoke the scripts they write in class. The course presents a number of practical examples that demonstrate how DRV scripting can be leveraged to improve the chip design process.

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Learn how to leverage the full power of Calibre nmDRC and Calibre nmLVS by attending the ‘Calibre Fundamentals: Performing DRC/LVS’ course. This course will teach you to effectively use Mentor Graphics Calibre nmDRDC and Calibre LVS software in your layout verification flow and will empower you to analyze DRC and LVS results successfully in coordination with a layout editor. The lecture modules will guide you through the various concepts underlying state-of-the-art layout verification techniques and specific aspects of the Calibre nmDRC and Calibre nmLVS toolset.

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This course will teach you to effectively write and maintain Calibre nmDRC and nmLVS rule decks for your semiconductor processes. In this class, you will extensively study the Standard Verification Rule Format (SVRF) language used in Calibre rule decks. The lecture modules will guide you through the various concepts underlying state-of-the-art layout verification techniques and specific aspects of the Calibre toolset. Hands-on lab exercises will reinforce lecture topics and provide you with rule writing experience under the guidance of our industry expert instructors.

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This course will help you unleash the powers of TVF to make your SVRF files more compact, easier to maintain, and more powerful. Using several examples, you will learn how to incorporate TVF functionality into your rule files to make writing SVRF rules easier.

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This course presents the most in-depth coverage of these topics available, extending your knowledge base far beyond existing documentation. Attendees should see immediate ROI in terms of both ramp-up time with the Calibre xRC tools and effectiveness.

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