Intel’s Instruction Set Architecture (ISA) continues to evolve to improve functionality, performance and the user experience. Featured below are planned extensions to the ISA that are new as well as those being planned for enhancements in future generations of processors. By publishing these extensions early, Intel helps ensure that the software ecosystem has time to innovate and come to market with enhanced and new products when the processors are launched.
- Getting
Started - Intel® AVX
- Intel® SGX
- Intel® MPX
- Intel® SHA
Extensions - Support
Forums
Overview
- Intel® Architecture Instruction Set Extensions Programming Reference (PDF) covers new instructions slated for future Intel processors.
- Details of the current architecture and programming environment of the Intel® 64 and IA-32 architectures can be found in the Intel®64 and IA-32 Architectures Software Developer Manuals.
Tools & Downloads
- Intel® Software Development Emulator (Intel® SDE)
This version includes support for:
- Intel® AVX-512, Intel® Secure Hash Algorithms Extensions and Intel® Memory Protection Extensions (Intel® MPX) instructions being introduced in future generation Intel processors
Product Overview | Download
- Intel® Architecture Code Analyzer
The Intel® Architecture Code Analyzer helps you conduct quick analysis for Intel® Advanced Vector Extensions before processors with these instructions are actually available.
Product Overview | Download
- Intel® C++ Compiler
The Intel® C++ Compiler is available for download from the Intel® Registration Center for all licensed customers. Evaluation versions of Intel® Software Development Products are also available for free download.
- Intel Intrinsics Guide
The Intel Intrinsics Guide is an interactive reference tool for Intel intrinsic instructions, which are C style functions that provide access to many Intel instructions – including Intel® Streaming SIMD Extensions (Intel® SSE), Intel® Advanced Vector Extensions (Intel® AVX), and more – without the need to write assembly code.
- Gcc Compiler
The gcc compiler and glibc library supporting Intel® AVX, Intel® AVX2, Intel® AVX-512 and Intel® MPX instructions are available for download under GPL from the Intel Software Development Emulator page.
Intel® Advanced Vector Extensions (Intel® AVX)
The need for greater computing performance continues to grow across industry segments. To support rising demand and evolving usage models, we continue our history of innovation with the Intel® Advanced Vector Extensions (Intel® AVX) in products today.
Intel® AVX is a new-256 bit instruction set extension to Intel® SSE and is designed for applications that are Floating Point (FP) intensive. It was released early 2011 as part of the Intel® microarchitecture code name Sandy Bridge processor family and is present in platforms ranging from notebooks to servers. Intel AVX improves performance due to wider vectors, new extensible syntax, and rich functionality. This results in better management of data and general purpose applications like image, audio/video processing, scientific simulations, financial analytics and 3D modeling and analysis.
Intel® Advanced Vector Extensions 512 (Intel® AVX-512)
In the future, some new products will feature a significant leap to 512-bit SIMD support. Programs can pack eight double precision and sixteen single precision floating numbers within the 512-bit vectors, as well as eight 64-bit and sixteen 32-bit integers. This enables processing of twice the number of data elements that IntelAVX/AVX2 can process with a single instruction and four times the capabilities of Intel SSE.
Intel AVX-512 instructions are important because they open up higher performance capabilities for the most demanding computational tasks. Intel AVX-512 instructions offer the highest degree of compiler support by including an unprecedented level of richness in the design of the instruction capabilities.
Intel AVX-512 features include 32 vector registers each 512-bit wide and eight dedicated mask registers. Intel AVX-512 is a flexible instruction set that includes support for broadcast, embedded masking to enable predication, embedded floating point rounding control, embedded floating-point fault suppression, scatter instructions, high speed math instructions, and compact representation of large displacement values.
Intel AVX-512 offers a level of compatibility with Intel AVX which is stronger than prior transitions to new widths for SIMD operations. Unlike Intel SSE and Intel AVX which cannot be mixed without performance penalties, the mixing of Intel AVX and Intel AVX-512 instructions is supported without penalty. Intel AVX registers YMM0–YMM15 map into Intel AVX-512 registers ZMM0–ZMM15 (in x86-64 mode), very much like Intel SSE registers map into Intel AVX registers. Therefore, in processors with Intel AVX-512 support, Intel AVX and Intel AVX2 instructions operate on the lower 128 or 256 bits of the first 16 ZMM registers.
More information about the details about Intel AVX-512 instructions can be found in the blog "AVX-512 Instructions". The instructions are documented in the Intel® Architecture Instruction Set Extensions Programming Reference (see the "Overview" tab on this page).
- Technical Content
- Blogs