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High-speed Successive-Approximation Analog-to-Digital Converter
With broad-market demand, like high-speed data link, the extension of monolithic high-speed analog-to-digital converter (ADC) is needed. Meanwhile,
low power dissipation is also a stringent requirement as portable products are becoming more and more popular, in which the batteryโs lifetime is the most critical specification. Also, because of
the integration of massive amounts of analog blocks as well as digital blocks, it is one of the most important cost issues to remove heat produced on chip.
The goal of this research is to investigate methods to reduce the power consumption of high-speed data converters A New high-speed successive-approximation (SAR) ADC will be presented that realizes lower power consumption, particularly saves 50% switching power compared with other time-interleaved SAR ADC. A 6-bit pipelined SAR ADC is designed to verify the proposed architecture.
Major Advisor: Gabor Temes
Committee: Un-Ku
Moon
Committee: Raviv Raich
Committee: Thinh
Nguyen
GCR: Bo Zhang
Kelley Engineering Center (campus map) |
|
4107 |
|
Nicole Thompson |
|
1 541 737 3617 |
|
Nicole.Thompson at oregonstate.edu |
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Sch Elect Engr/Comp Sci |
Oregon State University
Corvallis, OR 97331
541-737-1000
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