Last of three parts: Blurring the lines between packaging and manufacturing; progress on cross-disciplinary test and tools; issues in packaging, interconnect and test; who’s in charge and driving changes; why tools are lagging for creating TSVs; who owns what; debate over whether the supply chain will grow or shrink.

Second of three parts:Starting points for stacking; where standards are needed; 2.5D vs. 3D stacks; the role of test; the challenge of interconnects; potential power shifts in terms of who’s in control.

First of three parts: The growing need for standards; questions about cost and business relationships; new terminology; who’s responsible when something goes wrong.

Last of three parts: Stress effects from TSVs; testing stacked die; simplifying design rules and shifting from what’s not allowed to what is; the effect of 450nm and re-use on total cost.

Second of three parts: Improving information exchange; the impact of software; dark silicon; through-silicon vias and electrical effects; stacking die in 2.5D and 3D configurations; testing issues; DFM challenges; the limitations of interposers.

First of three parts: Risks of early adopters; tighter coupling of design and manufacturing; expected yields at 20nm and in stacked die; effects of double-patterning and variability; new rules and PDKs.

Last of three parts: The impact of 3D stacking and 3D structures; business changes and commoditization; competitive concerns; multisourcing at the leading edge.

Second of three parts: Risk and return on investment; big chipmakers vs. midsize companies; disaggregation vs. re-aggregation; the impact of 2.5D and 3D stacking.

First of three parts: Where handoffs make sense; big customers dictate the process spec; challenges with IP; role of the ecosystem.

Last of three parts: The growing importance of DFM; challenges in 3D stacking; trust and the sharing of data; who owns the problem?

Although mask makers have made masks for decades, reducing their defectivity remains a challenge. Why? The simple answer is their reflectivity and the process of making EUV mirrors.

Mentor Graphics and Samsung announce a yield-improvement approach that’s based on mined test data.

Participants at the 2011 International Workshop on EUVL — representing universities, national labs, tool suppliers and chip manufacturers — discussed ways to address current technical challenges for inserting EUVL into high-volume manufacturing.

Executives from GlobalFoundries, Microchip, STMicroelectronics, Freescale, Intel, Altera, MIPS, Xilinx, MoSys, and Mentor offered their opinions on the future challenges facing the semiconductor industry, at the Semico Summit, held in early May in Phoenix.

EUV Lithography expert Vivek Bakshi provides his roundup of EUV-related developments at the SPIE Advanced Lithography conference.

Using feedback mechanisms among a variety of EDA tool flows would allow designers to optimize incremental tapeouts to the benefit of the entire design-manufacturing ecosystem.

Semiconductor technologists face a crossroads at the 14nm node, when partially depleted, planar transistors are unlikely to deliver improvements in performance and power. Technologists at the recent International Electron Devices Meeting (IEDM) in San Francisco debated the relative merits of FinFETs (tall) versus extremely thin silicon on insulator, or ETSOI (thin).

Qualcomm CDMA Technologies said it will not use a high-k/metal gate (HKMG) process for most of the chips it makes at the 28nm node, sticking with a poly/SiON gate stack. The company described the rationale behind the strategy – which because of Qualcomm’s size will have a major impact on the foundry business — at the 2010 International Electron Devices Meeting (IEDM) held in San Francisco.

The technology competition to supply the source of EUV radiation for the next-generation lithography tools has long been divided between the laser-produced plasma (LPP) approach, favored by Cymer Inc. (San Diego) and Gigaphoton Inc. (Oyama, Japan), and the discharge-produced plasma (DPP) method supported by Xtreme Technologies GmbH (Aachen, Germany).

Soitec COO Paul Boudre discusses what will be the best solution for 20nm – fully depleted silicon on insulator or bulk 3D transistors? The answer will likely include both.

Just how easy is to move designs from one foundry to another? It depends who you ask.

What problems are we likely to face at future nodes and with 3D structures?

Just how real is 3D stacking and what are the main hurdles that need to be solved.

Karen Savala, president of SEMI Americas, looks at what’s new at Semicon this year, how the show is changing and what to look out for.

Juan Rey, senior director of engineering for Mentor Graphics’ Design To Silicon Division, talks about 3D stacking and 3D structures on chips.

Jonathan Davis, executive vice president of SEMI, drills down into the state of the chip industry, what’s driving the changes and what the big issues are for manufacturing and design in the future.

Bettina Weiss, who heads SEMI’s solar effort, talks about what’s new at Semicon and Intersolar North America, how far the industry has progressed and what stands in the way of widespread adoption of solar technology.

Michael Buehler-Garcia, director of Calibre Design Solutions marketing at Mentor Graphics, talks about the challenges in building 2.5D stacks and how testing them will become a major headache.

The SEMI consensus forecast estimates equipment sales rising 12% to $44.3 billion in 2011, despite a brief period of capacity consolidation.

Intel’s process architect and integration specialist, Mark Bohr, talks about the future of chip design and manufacturing and what’s driving some spectacular changes. “The same Tri-Gate structures will be used on our high-performance processors as well as our low-power and SoC types of products,” Bohr said.

The burgeoning market for chemicals and materials used in solar cells and modules is expected to grow to $16.9 billion in 2015, up from $6.5 billion in 2010, according to a jointly prepared report from  SEMI and Linx-AEI Consulting.

Global…